This invention relates generally to the field of packaging semiconductor devices. More particularly, this invention relates to methods and apparatus for packaging integrated circuits using selective application of solder bumps.
Semiconductor integrated circuits have traditionally been packaged using wirebonding technology. In this technology, as illustrated in FIG. 1, a semiconductor die 10 is attached to a chip carrier 14 (of any of a number of different configurations, e.g., dual inline package) using an adhesive. The die 10 has a plurality of conductive wirebonding pads such as pad 18 arranged around the periphery of the die 10. These wirebonding pads 18 are connected to circuitry on the die 10 to make electrical connections such as power, ground and various signal connections, depending on the die""s circuitry. In order to make these connections available outside of the die, pads such as 18 are electrically connected using fine wires such as 22 that are bonded to pads 18 and to corresponding wirebonding pads 28 on the chip carrier 14. The chip carrier 14 then provides interconnections to other circuitry by use of solder pins or pads connected to the chip carrier""s pads such as 28.
Such wirebonding techniques have been used successfully for many years and remain in common use today. However, the above wirebonding technique has limitations in that the wirebonding pads must usually be arranged along the periphery of the semiconductor die. This limits the number of connections that can be made. Also, power and ground connections provided to circuitry located in a central area of the die may be a significant distance from the wirebond pad 18. As semiconductor processing technology improves, the conductors used to carry such power and ground connections can be extremely fine resulting in unacceptable impedance between the point of the wirebond and the circuitry being powered.
These problems are addressed in a solder bump die connection technology illustrated in FIG. 2. This technology, although originally pioneered in the 1960s, has been more widely adopted over the last several years. In this technology, solder pads are situated at any given location of a semiconductor die 38 and corresponding pads provided on a chip carrier or other substrate 44 to which the die is to be connected. Bumps of solder such as 46 are then screened onto the die 38 at the location of the die""s solder pads through a mask that permits solder to only be deposited in the desired locations. The die 38 is then set into place on the substrate 44 aligning the solder pads of die 38 with those of substrate 44, and the assembly is heated to cause the solder to flow and create both a mechanical and electrical connection.
With this improved solder bump technology, much higher density can be achieved and the electrical interconnections can be made at virtually any location on the die""s surface. However, as the density of circuitry provided on the die increases, an additional problem is encountered.
When the die contains circuitry made using a relatively low resolution process (e.g., greater than 0.09 micron line technology), and the die contains logic circuitry that can be selectively activated or deactivated (e.g., to provide redundancy, selective functionality or selective configuration), it is often sufficient to simply disable clocks to the circuitry that is to be disabled. However, as line resolutions get smaller, e.g., below 0.09 microns, the power consumption of the logic circuitry due to leakage currents may be a significant contribution to overall power consumption. Due to variations in the actual circuit configuration, of course, the above line sizes should be considered only exemplary of the potential problem.
The present invention relates generally to a semiconductor packaging. Objects, advantages and features of the invention will become apparent to those skilled in the art upon consideration of the following detailed description of the invention.
In one embodiment consistent with the present invention, selective application of solder bumps is used in mounting an integrated circuit die to a package such as a chip carrier or other substrate. Solder bumps are selectively applied in a solder bump integrated circuit packaging process so that portions of a circuit can be effectively disabled. The bumps may be selectively applied using multiple solder masks, one for each pattern of solder bumps desired or can be otherwise applied in multiple patterns depending upon which portions of the circuitry are to be active and which are to be disabled.
A method, consistent with an embodiment of the present invention, of connecting an integrated circuit die to a substrate, includes identifying a block of circuitry to be disabled within the integrated circuit die; applying a pattern of solder bumps to one of the die and the substrate, the pattern of solder bumps excluding at least one solder bump used for connection to the block of circuitry; placing the integrated circuit die on the substrate with solder pads on the die aligned with corresponding solder pads on the substrate and with the pattern of solder bumps disposed between the die and the substrate; and heating the solder bumps to cause the solder to flow and form electrical connections between the substrate and the die.
Another method, consistent with an embodiment of the present invention, of applying solder bumps for soldering a substrate to an integrated circuit die, includes identifying a block of circuitry on the integrated circuit die that is to be disabled; and applying a pattern of solder bumps to one of the die and the substrate, the pattern of solder bumps excluding at least one solder bump used for connection to the block of circuitry that is to be disabled.
Another method, consistent with an embodiment of the present invention, of configuring functionality of an integrated circuit die, includes identifying a block of circuitry to be configured by selectively making an electrical connection between a substrate and the integrated circuit die; applying a pattern of solder bumps to one of the die and the substrate, the pattern of solder bumps selectively excluding at least one solder bump used for connection to the block of circuitry; placing the integrated circuit die on the substrate with solder pads on the die aligned with solder pads on the substrate and the pattern of solder bumps disposed therebetween; and heating the solder bumps to cause the solder to flow and form electrical connections between the substrate and the die.
An integrated circuit device, consistent with certain embodiments of the present invention has an integrated circuit die having a plurality of solder pads used for conveying signals to and from the die, the integrated circuit having a plurality of blocks of circuitry. A substrate has a plurality of solder pads corresponding to at least a portion of the integrated circuit die""s solder pads. A plurality of solder bumps connect the substrate to the integrated circuit die, and at least one of the blocks of circuitry is configured by virtue of omission of a solder bump for at least one connection between the substrate and the at least one of the plurality of blocks of circuitry.
Many variations, equivalents and permutations of these illustrative exemplary embodiments of the invention will occur to those skilled in the art upon consideration of the description that follows. The particular examples above should not be considered to define the scope of the invention.